Embodiments of the present disclosure relate generally to semiconductor devices and, more particularly, to semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same.
Regarding fabrication processes for semiconductor devices, various technologies have been proposed to increase the number of integrating elements such as transistors in a limited area of a semiconductor substrate to improve the throughput of the semiconductor devices. For example, dynamic random access memory (DRAM) technologies have been developed to create a unit memory cell that contains a single cell transistor and a single cell capacitor in a unit area of about 4F2 (“F” denotes a minimum feature size). To make this work, planar transistors that were used as the cell transistors have been increasingly replaced with vertical transistors.
Each of the vertical transistors may be configured to include a drain region and a source region respectively disposed in an upper portion and a lower portion, or respectively disposed in a lower portion and an upper portion of an active pillar, and a gate electrode disposed on a sidewall of the active pillar between the drain region and the source region. When the vertical transistors are employed as the cell transistors of the DRAM devices, the drain regions in the active pillar may be electrically connected to bit lines and the source regions in the active pillars may be electrically connected to the cell capacitors acting as data storage elements. Thus, one of the cell capacitors and the bit lines may be formed in a bulk region of the semiconductor substrate. For example, when the drain regions of the vertical transistors are formed in the lower portions of the active pillars, the bit lines may be formed in the semiconductor substrate thereby having buried structures.
If bit lines of the DRAM devices are to be buried in the semiconductor substrate, complicated processes ensue, since it may be difficult to form the buried bit lines in the semiconductor substrate while maintaining electrical connectivity to the drain regions of the active pillars.